The present disclosure herein relates to a simulation system, and more particularly, to a multi-core simulation system and method based on a shared translation block cache.
As various next generation smartphones, portable devices, and smart TVs, etc., emerge, a technique related to development of a fusion processor, in which a multi-core processor and a graphic accelerator are integrated, is being proposed to support for processing various tangible graphics in 2D/3D.
A processor being currently used in a smartphone has evolved from a typical single core to current dual cores, and when viewed from processor development and a trend of device miniaturization, it is expected to evolve to a multi-core type of quad-cores or more. In addition, in a next generation mobile terminal, a multi-core processor, in which dozens to hundreds processors are integrated, is expected to enable biometrics and augmented reality.
A typical processor speeds up a clock to improve performance, but there is a limitation in that it is difficult to raise a speed more since power consumption becomes greater and heat increases accordingly. Since a multi-core processor proposed to address such a limitation includes several cores, an individual core may operate at a lower frequency and power consumed by a single core may be dispersed to other cores.
Since mounting a multi-core processor is the same as mounting two or more central processing units, when a task is performed with a program for supporting the multi-core processor, the task may be performed faster than a case with a single core processor and performance higher than that of the single core processor may be secured in a task such as compression and reconstruction of a video, execution of high specification game, or realization of augmented realty in a next generation mobile terminal, which basically performs multimedia-processing.
In order to develop an optimal SoC structure based on the multi-core processor, a design methodology of a virtual platform-based system level is required to analyze early a function and performance of an SoC at an upper level, and the most important core element in designing a virtual platform is to design an emulator, which models a multi-core function at a function-accurate level.